1. Field of the Invention
The present invention relates to a high voltage transistor in a flash memory device and, more specifically, to a high voltage transistor in a flash memory device that can obtain a uniform and constant saturation current regardless of the number of a contact hole in a source/drain junction having a double diffused drain (hereinafter, referred to as “DDD”) structure consisting of a high-concentration impurity region and a low-concentration impurity region surrounding the high-concentration impurity region.
2. Discussion of Related Art
Semiconductor memory devices may be classified into random access memory (RAM) products, which are volatile, lose data as time goes and are fast to read from and write to, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and read only memory (ROM) products, which retain data once they are inputted, but are low to read from and write to. Of these ROM products, there is an increasing demand for an electrically erasable and programmable ROM (EEPROM) or a flash memory to/from which data can be inputted/outputted electrically. The flash memory device is an advanced version of EEPROM, which can be electrically erased at high speed, while being not removed from a circuit board. The flash memory device has advantages that the manufacturing cost per unit memory is cheap due to a simple memory cell structure and a refresh function for retaining data is unnecessary. The flash memory is, however, disadvantageous that a write and erase rate of data, several hundreds of □ to several ms, is significantly lower than several tens of ns of the RAM products.
When viewing a flash memory device from a circuit's viewpoint, the operating speed is high since each memory cell can be independently controlled. The flash memory cell can be classified into a NOR type that is large in cell area since one contact is necessary every two cells, and a NAND type that is advantageous in higher degree of integration since several memory cells can be controlled as a single bundle.
In an NAND type flash memory device, a cell transistor that is operated by an external peripheral circuit has a structure in which a first gate that is floated and a second gate that controls the first gate are stacked. A program operation of a cell is performed as some of channel hot electrons are injected into the first gate through a tunnel oxide film by means of fowler-nordheim (F-N) tunneling or hot electron injection. In order to perform such program operation, a voltage of 0V is applied to a bulk substrate and a high voltage of 20V or more is applied to the second gate that is provided as a word line of a cell array. In this state, a voltage of 10 M V/cm or more is introduced to both ends of the tunnel oxide film, so that electrons are injected from the substrate to the first gate. Meanwhile, in order to perform an erase operation of the cell, a voltage of OV is applied to the second gate and a voltage of −20V is applied to the bulk substrate, so that electrons injected into the first gate are discharged toward the substrate by a voltage difference between the first gate and the substrate.
As such, the NAND type flash memory device needs an external circuit for driving the cell. This circuit consists of a transistor having a high voltage junction breakdown voltage of usually 20 V or more. A high voltage generated by such a transistor is transferred to the word line of the cell array used as the second gate along the power line made of a conductor such as a metal, thereby programming the cell. As described above, the process of fabricating the transistor for forming the high voltage junction breakdown voltage and transferring the high voltage to the word line is very important. Such a transistor is usually referred to as a ‘high voltage transistor’ and is formed in a region differentiated from a low voltage transistor whose operating voltage is about Vcc.
FIG. 1 is a layout view illustrating a high voltage transistor in an NAND type flash memory device in a related art, FIG. 2 is a cross-sectional view illustrating the high voltage transistor taken along lines II–II′ in FIG. 1, and FIG. 3 is a cross-sectional view illustrating the high voltage transistor taken along lines III–III′ in FIG. 1.
Referring to FIG. 1, FIG. 2 and FIG. 3, an isolation film 12 is formed in a given region of a semiconductor substrate 11 by means of a common isolation process, thereby defining an active region in which a cell transistor, a high voltage transistor, a low voltage transistor, etc. will be formed. In the drawings, however, it is to be noted that only the active region in which the high voltage transistor will be formed is shown for simplicity. A threshold voltage control layer is formed on the semiconductor substrate 11 in the active region by injecting an impurity ion in order to optimize the threshold voltage of a channel transistor. A gate insulating film 13 is then formed on the resulting surface. After a conductive material such as polysilicon into which an impurity is doped is deposited on the gate insulating film 13, the material is patterned by a photolithography process, thus forming a gate electrode 14. A low-concentration impurity region 20 is formed in a semiconductor substrate 11 at both sides of the gate electrode 14 by means of a low-concentration impurity ion implantation process. The low-concentration impurity region 20 is formed using an impurity ion having a different conductive type from the semiconductor substrate 11. An interlayer insulating film 15 is then formed on the entire structure including the low-concentration impurity region 20. A portion of the interlayer insulating film 15 is etched to form a contact hole 16 through which a central portion of the low-concentration impurity region 20 is exposed. The reason why the contact hole 16 is formed at the central portion of the low-concentration impurity region 20 is that a junction breakdown voltage can be increased if the distance between a high-concentration impurity region to be formed later and the gate electrode 14 and the distance between the high-concentration impurity region and the isolation film 12 are kept constant. Thereafter, an impurity ion of a higher concentration than the low-concentration impurity region 20 is implanted into the low-concentration impurity region 20 exposed through the contact hole 16 by means of a plug mask process and a plug ion implantation process, so that a high-concentration impurity region 21 is formed in the low-concentration impurity region 20. A source/drain junction 221 of a DDD structure having the high-concentration impurity region 21 and the low-concentration impurity region 20 surrounding the high-concentration impurity region 21 is thereby completed. At this time, the high-concentration impurity region 21 is formed using an impurity ion having the same conductive type as the low-concentration impurity region 20. A conductive material such as polysilicon, tungsten, etc. is filled into the contact hole 16 to form a contact plug 17. A metal wire 18 electrically connected to the contact plug 17 is formed on the interlayer insulating film 15.
In general, in the case of a high voltage transistor used in an NAND type flash memory device, as the number of portions contacting the source/drain junction 221 become many, i.e., the number of the contact hole 16 becomes many, the transistor has the property that the saturation current is reduced, as shown in FIG. 4. FIG. 4 is a graph shown to explain a saturation current characteristic depending on the number of a contact hole in a typical high voltage transistor. Actually, in a high voltage transistor used in a page buffer circuit in an NAND type flash memory device, only one contact hole 16 is formed in the source/drain junction 221, as shown in FIG. 1. A total area of the source/drain junction 221 can contain at least three contact holes. In the high voltage transistor used in the page buffer circuit, however, as the metal wire 18 cannot but pass the high voltage transistor region, it is difficult to additionally form other contact holes. As such, as one contact hole 16 is formed at the central portion of the source/drain junction 221, a current density to pass the gate electrode 14 is high at its center and low toward its edge. Accordingly, in the high voltage transistor used in the page buffer circuit, the current density to pass the gate electrode becomes irregular. Due to this, not only a constant saturation current cannot be obtained, but also the performance of a device is degraded and error in design simulation is caused due to reduction in saturation current.